1. Field of the Invention
The apparatus of the present invention generally relates to data processing systems and more particularly to a priority network for providing transfer cycles over a common bus coupling a plurality of units in such system.
2. Description of the Prior Art
The apparatus of the present invention is an improvement to the priority logic described in U.S. Pat. No. 4,096,569, issued June 20, 1978 which was an improvement to the priority logic described in U.S. Pat. No. 4,030,075, issued on June 14, 1977, which patents are incorporated herein by reference. Such priority logic included in the priority network of such patents is distributed to each of the units coupled to the common bus so as to enable priority determination and thereby the granting of a bus cycle to the highest priority requesting unit without the need for a bus monitor, for example in a central processor, which may be one of the units coupled to the bus. Each such priority logic includes three bistable elements, one of which indicates an internal request for use of the bus, another of which indicates on the bus that an internal request has been made, and a further one is provided to indicate that a bus cycle has been granted for this unit. Only one such unit's priority logic may have its so-called bistable element indicate that a bus cycle has been granted. The priority logic in more than one unit may have their so-called request bistable elements set to indicate that they desire bus cycles. Typically, the unit transferring information to another unit receives a response. Such response may either be a signal indicating that the information transferred has been accepted (an ACK signal), that the information transferred has not been accepted (a NACK signal), or a signal indicating that the information has not been accepted by the receiving unit but that such receiving unit will be enabled to so receive such information possibly during the next bus cycle (a WAIT signal). In response to either of these signals, it has been shown in such aforementioned U.S. Pat. No. 4,030,075 that the so-called grant bistable element which has been set, may be reset so that each of the units on the bus may again in parallel attempt to gain access to the bus, thereby avoiding a situation where one unit which had previously been granted access to the bus is unable to gain such access until its receiving unit responds by indicating it has received such information. In such aforementioned U.S. Pat. No. 4,030,075, it was shown that the so-called ACK or NACK signals would also cause the so-called request bistable element to be reset or cleared. However, in so resetting such request bistable element, it is important that only the unit which had its grant bistable element set have its request bistable element reset. Otherwise, each of the request bistable elements in each of the units would be reset. This would then require that each of such units that did not have its grant bistable element set have its so-called request bistable element set again. In order to avoid such operation, it was necesssary to include logic by which the unit so setting its so-called grant bistable element retain a history of such action. This required additional logic in the system and, accordingly, it was considered desirable to eliminate such excess logic thereby reducing the space and power requirement in the system while still maintaining priority logic which was distributed, asynchronous in nature and which retain the speed required of the system.
Accordingly, it was the object of the U.S. Pat. No. 4,096,569 to provide improved priority logic for use in a data processing system in which a plurality of units are coupled over a common bus. In the U.S. Pat. No. 4,096,569, each such priority logic comprised a first bistable element for asynchronously indicating that a representative unit is ready to transfer information over the bus, a second bistable element responsive to the first bistable element responsive to the first bistable element for generating a first signal on the bus indicating to each of the units that the representative unit is ready to transfer information over the bus, apparatus responsive to the second bistable element in each of the units having a higher priority than the representative unit for indicating that the representative unit is in the highest priority unit and a third bistable element responsive to the first signal generated by the second bistable element and an indication that there is no other higher priority unit ready to transfer information over the bus, for generating a second signal on the bus. Further, provide was apparatus which is responsive to the receipt of the second signal from the bus for generating a strobe signal for enabling the receipt of information from the representative unit and further apparatus which is responsive to the acknowledgement that the information has been so received, for disabling the third bistable element of the representative unit. Further, logic was also provided which is responsive to the disabling of the third bistable element for disabling the second bistable element of the representative unit, which is the only unit that had its third bistable element set.
The distributed tie-breaking network provides the function of granting bus cycles and resolving simultaneous requests for use of the bus. Under both the U.S. Pat. Nos. 4,096,569 and 4,030,075, priority is granted on the basis of physical position on the bus and the lowest priority being given to the last unit on the bus. The logic to accomplish the tie-breaking function is distributed identically among all units connected to the bus. In a typical system, the memory is granted the highest priority and the central processor unit (CPU) is granted the lowest priority because it has the lowest real time constraints with the other units being position on the basis of their performance requirements.
However, the CPU is the heaviest user of the common bus and in order to improve system performance, it is desirable to position it as close as possible to the memory. Accordingly, it is the primary objective of the present invention to provide improved priority logic which will allow a lowest priority unit to be physically positioned on the common bus at a position other than in the last unit position.